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RTLvision PRO (TM) provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog. It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.
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GateVision® is a standalone graphical netlist analyzer that allows intuitive design navigation, schematic viewing, logic cone extraction, interactive logic cone viewing, and design documentation. GateVision's easy-to-read schematics and schematic fragments provide excellent debug support and accelerate the debug process. GateVision is designed to meet today's complex system-on-chip demands and seamlessly fits into any EDA design environment where design data are stored in either Verilog or EDIF netlist format.
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GateVision® Demo
GateVision® Hebrew Article
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Spice circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest level of components: the transistors, capacitors, resistors and even the interconnect, that combine to produce, for example, an IC. But for all but the most trivial design, Spice files are difficult to read. SpiceVision generates circuit schematics on screen and speeds up debugging and project development. The SpiceVision product family helps to solve design problems in: Digital Circuits, Mixed-Signal ASICs, Analog Circuits, Printed Circuit Boards and MEMS.
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SpiceVision® Demo
SpiceVision® Hebrew Article
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SGvisionPRO (TM) is a new tool to analyze mixed level descriptions, both top level structures described in Verilog and lower level structures described via SPICE, can be debugged in a single integrated environment. To optimize or debug a device a designer may choose to work at transistor-level for critical areas such as IP/Library components and analog blocks, while staying at gate-level for other areas of the design. Debugging such a design has previously required separate tools: with SGvision PRO, it is now possible to see the schematics and traverse the signal flow of both the gates and the transistors in the same window, improving understanding of the circuits and accelerating analysis and debugging.
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Concept Engineering's Nlview Widgets are a family of schematic generation and viewing software components) GUI building blocks (that can be easily used and customized within the most popular GUI development environments such as: Tcl/Tk, Java, MFC, Qt and Perl/TK. The Nlview) Widgets give software teams unparalleled reliability, flexibility and performance, so that they can realize GUIs for EDA products with shorter design cycles and lower development and maintenance cost.
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Nlview Java Demo
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StarVisionTM PRO: RTL-Level, Gate-Level and SPICE-Level in one Integrated Debugging Cockpit
StarVision PRO provides engineers
with the ability to quickly and
easily understand and debug
mixed-mode designs and to integrate IP
building blocks into their complex SoCs
and ICs..
All-in-One - Due to the increasing use
of building blocks in SoC design, engineers
need to work at different design levels
(RTL, gate, transistor, analog, parasitic) as
well as with different design languages and
netlist formats. To support this challenge,
Concept Engineering developed StarVision
PRO, an integrated debugging cockpit for
mixed-signal and digital design that makes
analysis and debugging of complex SoC
and IC designs easy and more transparent.
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StarVisopnPro live Demo
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